1. Technical Field of the Present Invention
The present invention generally relates to CMOS technology and very-large-scale integrated circuits and more specifically, to methods and structures that enable the use of high-mobility crystalline planes in double-gate CMOS technology.
2. Description of Related Art
Complementary Metal Oxide Semiconductor (CMOS) has been the technology of choice for Very-Large-Scale Integration (VLSI) wherein literally tens of millions of transistors (or more) can be fabricated to form a single integrated circuit.
In order to provide greater numbers of transistors with greater speed, one option that has been proposed in the art is to utilize freestanding silicon rails as the body for the transistor. These bodies, or so-called xe2x80x98finsxe2x80x99, are perpendicular to the plane defined by the wafer surface. See for example U.S. Pat. No. 6,252,284 to Muller, et al. Double-gated transistors constructed with such fins can provide lower leakage currents and are scalable to smaller gate lengths. See Tang et al, xe2x80x9cFinFETxe2x80x94A Quasi-Planr Double-Gate MOSFET,xe2x80x9d 2001 IEEE International Solid State Circuits Conference, Paper 7.4.
It is further understood that in semiconducting crystals such as silicon, the mobility of holes and electrons is a function of the crystalline plane in which the channel of the transistor is formed. For instance in silicon, electrons have their greatest mobility in {100}-equivalent planes while holes have their greatest mobility in {100}-equivalent planes, as discussed by Takagi, et al., xe2x80x9cOn the Universality of Inversion Layer Mobility in Si MOSFETs: Part Ixe2x80x94Effects of Substrate Impurity Concentration,xe2x80x9d 1994 IEEE Trans. on Electron Devices, V. 41, No. 12, December 1994, pp. 2357-2368. Other types of semiconductor substrates (e.g. gallium arsenide) typically have differing electron/hole mobilities in different planes.
As a practical matter it has proven to be difficult to form NFETs and PFETs on different planes without decreasing device density and/or increasing process complexity. For example, in U.S. Pat. No. 4,933,298 silicon islands on a SOI substrate are selectively masked and recrystallized to form islands of different crystal orientation, which increases process cost. In U.S. Pat. No. 5,317,175 the respective n and p devices are formed in separate areas of the substrate, orthogonal to one another, sacrificing density. In U.S. Pat. No. 5,698,893, as well as Japanese Published Patent Applications JP 1264254A and JP 3285351A, the respective devices are formed on horizontal and vertical surfaces of the substrate; trench formation increases process complexity and expense.
It would, therefore, be a distinct advantage to provide freestanding semiconductor bodies with p-type and n-type transistors having channels in different channel planes, in a manner that adds a minimum of process complexity and loss in density.
In a first aspect, the invention comprises a MOS device, comprising first and second freestanding semiconductor bodies formed on a substrate, said first freestanding semiconductor body having a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of said second freestanding semiconductor body, said portions of said first and second freestanding semiconductor bodies having respective first and second crystalline orientations; a first gate electrode crossing over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle with respect thereto; a second gate electrode crossing over at least part of said first portion of said second freestanding semiconductor body at a non-orthogonal angle with respect thereto; and controlled electrodes disposed at least in portions of said first and second freestanding semiconductor bodies exposed by said first gate electrode and said second gate electrode, respectively.
In a second aspect, the invention comprises a CMOS device, comprising a first freestanding semiconductor body with a n-type channel region disposed on a first crystalline plane that has greater electron mobility than that of a second crystalline plane of said first freestanding semiconductor body, a first gate electrode that crosses over said channel region at a non-orthogonal angle with respect thereto; a second freestanding semiconductor body with a p-type channel region disposed on a second crystalline plane that has a greater hole mobility than that of said first crystalline plane of said first freestanding semiconductor body, and a second electrode that crosses over said channel region at a non-orthogonal angle with respect thereto.
In a third aspect, the invention comprises a method of forming a MOS device, comprising forming a first freestanding semiconductor body with a n-type channel region disposed on a first crystalline plane that has greater electron mobility than that of a second crystalline plane of said first freestanding semiconductor body, and a first gate electrode that crosses over said channel region at a non-orthogonal angle with respect thereto, and source and drain regions; and forming a second freestanding silicon body with a p-type channel region disposed on a second crystalline plane that has a greater hole mobility than that of said first crystalline plane of said first freestanding semiconductor body, a second electrode that crosses over said channel region at a non-orthogonal angle with respect thereto, and source and drain regions.
In a fourth aspect, the invention comprises a method of providing a densely integrated circuit comprising first and second FinFETs with channel regions disposed on first and second crystal planes, comprising the steps of orienting a semiconductor wafer at a given axis; forming a first set of mask shapes at a first azimuthal angle with respect to said given axis; forming a second set of mask shapes at a second azimuthal angle with respect to said given axis; forming FinFET bodies in said semiconductor wafer by etching portions of the wafer exposed by said first and said second sets of mask shapes; and forming gate electrodes over said FinFET bodies at orientations that are favorable for lithographic control.